As the trend towards ever increasing capacity of semiconductor memories continues, new designs are necessary to conserve space on the chip without compromising performance. As smaller and smaller memory cells become feasible, the problem of effectively accessing the cells with word lines and bit lines without adding significantly to the size of the chip, becomes more challenging.
Conventional DRAM chips employ millions of memory cells arranged in one or more arrays of rows and columns, with bit lines running parallel to the columns and word lines running parallel to the rows. Each memory cell is comprised of an access transistor (e.g., an NFET) and a capacitor such as a trench capacitor for storing charge corresponding to a data bit. The memory cells are typically located at the intersections of the word lines and bit lines. The gate electrode of each access transistor is electrically connected to the associated word line while the transistor's drain terminal is connected to the associated bit line.
In what is known as a folded-bit line architecture, "true" memory cells are located in close proximity to corresponding complementary memory cells. The true cells are connected to true bit lines and the complementary cells are connected to complementary bit lines. A true bit line and an adjacent complementary bit line form a bit line pair. The bit line pair is typically connected at one end to a sense amplifier. The term "column" is sometimes used herein to refer to a bit line pair.
Prior to reading data from a true cell, the true and complementary bit lines are precharged with a certain precharge voltage, and then left floating at that voltage. To read from the true cell, the access transistor is switched on, thereby modifying the voltage level on the true bit line due to charge sharing with the memory cell capacitor. The voltage on the complementary bit line remains at the precharge voltage, whereby a differential voltage is applied to the sense amplifier. The sense amplifier then amplifies the differential voltage to provide a solid logic level for readout and restore operations. Similarly, to read from a complementary cell, the true bit line is held at the precharge voltage while the word line coupled to the complementary cell is raised, whereby an analogous differential voltage is amplified by the sense amplifier.
A word line configuration designed to reduce memory cell access time (RC time constant of the word line) is referred to herein as a dual word line configuration. A dual word line consists of a master word line running continuously across the entire memory cell array or subarray, and a number of local word lines, either connected to or separated from each other, each electrically connecting a predetermined number of memory cells in an associated row to one master word line. One master word line and multiple local word lines are used for each row of the array. Each master word line overlies the associated local word lines on a different vertically-spaced layer, with a suitable dielectric layer separating the two layers. The master word line is composed of a low resistivity metal such as aluminum whereas the local word lines are typically composed of highly doped polysilicon with a silicide layer on top. In what is referred to as a "stitched" architecture, the local word lines are electrically connected to the associated master word line by means of periodic electrical via hole contacts (stitches) between the layers. In what is known as a "segmented" dual word line architecture, word line drivers employing FET switches are used in place of the via hole contacts. With either approach, the total resistance in the path to any given memory cell is substantially reduced. With lower word line resistance, the RC time constant associated with each word line is reduced, thereby reducing memory cell access time. The segmented architecture has the additional advantage of reduced word line capacitance; however, a drawback to this configuration is the additional complexity and space required for the local word line drivers.
Recently, a high density DRAM referred to as a "diagonal bit line (DBL)" DRAM has been developed. With the DBL-type DRAM, the effective cell size is nearly 6F.sup.2, where F is the minimum feature size of the processing technology. An example of a diagonal bit line type DRAM is disclosed in an article entitled "FA 14.6: A 1 Gb DRAM for File Applications", by T. Sugibayashi et al., ISSC95/Session 14. That article discloses a DRAM using an open bit line architecture. The open bit line architecture, however, is more susceptible to noise-related problems than a folded bit line architecture.
Referring to FIG. 1A, there is shown a portion of a diagonal bit line type DRAM employing segmented dual word lines and folded bit lines. Each memory array in the DRAM is divided into multiple memory blocks such as B1, B2 and B3. Dual word lines such as WL.sub.i or WL.sub.y extend across multiple blocks and are driven by a main word line driver 93. Local word line drivers are disposed in areas L.sub.D between the blocks. As shown in FIG. 1B, each dual word line as WL.sub.i consists of a master word line MWL.sub.i and a number P of local word lines LWL.sub.1 -LWL.sub.p. A local word line driver LWD is coupled between each local word line and the master word line. Each local word line driver operates to drive the associated local word line to permit selective access to the cells coupled to that local word line.
Folded bit line pairs such as BLP.sub.j, BLP.sub.i, BLP.sub.y are each coupled to a respective sense amplifier within sense amplifier bank 92. Each pair as BLP.sub.j consists of a true bit line BL.sub.j and a complementary bit line /BL.sub.j. The bit lines run diagonally with respect to the word lines, changing direction at twist regions 33. Direction changes occur every K word lines, where K is typically 2.sup.N, e.g., eight, sixteen, thirty-two, sixty-four, etc. As shown in FIG. 2, the true and complementary bit lines of each bit line pair are vertically spaced from one another, alternatingly overlying and underlying one another. At each twist region 33, a three dimensional twist occurs such that the vertical positions of the true and complementary bitlines change with respect to one another. This three dimensional twist will be referred to herein as a vertical twist. At twist regions 33, a change in horizontal direction can also occur. In this case, the bit lines define zigzag-type patterns in the horizontal plane along the memory array.
An example of a memory cell array employing diagonal bit line cells and vertical twists for the bit lines is disclosed in co-pending U.S. patent application Ser. No. 08/884,853, attorney docket numbers 96E9190US and FI8960449, by John DeBrosse et al., filed Jun. 30, 1997, assigned to the assignee herein and incorporated herein by reference in its entirety (hereafter, the DeBrosse et al. application).
In the architecture of FIG. 1A, the zigzag patterns of the bit lines, in conjunction with the locations of the local word line drivers between memory blocks, results in wasted chip area in the regions A.sub.p at the edge of each memory block. The area penalty is a function of the bit line slant angle .THETA. of the pattern and the length D.sub.T of the vertical twist regions.
Accordingly, for high density memories employing diagonal bit lines, there is a need for an improved architecture in which the above-described area penalty is reduced or substantially eliminated, such that a smaller chip size for a given memory capacity can be realized.